IEEE based VLSI projects 2014

1.   Fast Radix-10 Multiplication Using Redundant BCD Codes Download
2.   Efficient Integer DCT Architectures for HEVC.Download
3.   A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values.Download
4.   A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant
      Circuits. Download
5.   An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator. Download
6.   Multifunction Residue Architectures for Cryptography.Download
7.   Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay.Download
8.   Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm.Download
9.   Recursive Approach to the Design of a Parallel Self-Timed Adder Download
10. Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Download
11. Statistical Analysis of MUX-Based Physical Unclonable Functions Download
12. 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands
      Scheduler Download
13. Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter Download
14. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip Download
15. On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays Download
16. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for
      DSRC Applications Download
17. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR
      Filter Implementation Download
18. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Download
19. A Method to Extend Orthogonal Latin Square Codes Download


 

Projects List

Multipliers :

1.  Radix-4 Booth Multiplier.
2.  Radix-8 Multiplier.
3.  Baugh wooley Multiplier.
4.  Signed and Unsigned Booth Multiplier.
5.  16-bit  Floating point Multiplier.
6.  Multiplication based on Vedic Mathematics.
7.  Power efficient vedic multiplier.
8.  Low Power Twin Precision Multiplier.
9. linear Convolution based on vedic mathematics.
10. Complex multiplier.
11. Square of a number based on vedic multiplication.
12. Multiplication based on both KCM and Vedic mathematics. 


Adders:

1.  16-bit  Ripple carry adder.
2.  32-bit  Ripple carry adder.
3.  16-bit  Carry Look ahead adder.
4.  32-bit  Carry Look ahead adder.
5.  carry save adder.
6.  carry select adder.
7.  Binary coded decimal adder.

Cryptography related :

1.  64-bit DES (Data encryption standard) Algorithm.
2.  Tripple DES Algorithm.
3.   128-bit AES (Advanced Encryption Standard) Algorithm.
4.   Analysis on asynchronous S-box.
5.   CORDIC Algorithm.
 

Softwares and Technologies in VLSI

Technologies :

1.  Front End
2.  Back End

Softwares :

In  Front End :

 1.    Modelsim
 2.    Xilinx
 
In Back End :

 1.   Digital schematic
 2.   Microwind

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