1. FPGA implementation of multi operand redundant adders
2. Multi bit Flip-Flop design for Area efficiency
3. Constant and high speed adder design using QSD number system
4. Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology
5. Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool
6. Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique
7. Implementation of JPEG2000 using DWT
8. High-Performance High-Valency Ling Adders
9. High speed vedic multiplier using barrel shifter
10. Design of FIR Filter Design Based on Faithfully Rounded Truncated MCM
11. Built in generation of functional broadside tests using a fixed hardware structure
12. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation.
13. A new approach to design fault coverage circuit with efficient hardware utilization for testing applications
14. A Common Boolean Logic(CBL) implementation for modified CSLA
15. Design of High Speed Vedic Square by using Vedic Multiplication Techniques
16. Realization of Basic Gates Using MUX in CMOS Design
17. MDC FFT/IFFT Processor With Variable Length
18. Short Bit-Width Twos Complement Multipliers
19. High speed carry save multiplier based linear convolution using Vedic mathematics
20. Implementation of OFDM System using IFFT and FFT
21. Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
22. A Verilog Model of Universal Scalable Binary Sequence Detector
23. Performance Evaluation of Complex Multiplier Using Advance Algorithm
24. FPGA Implementation of 2-D DCT Architecture for JPEG Image Compression
25. High speed Modified Booth Encoder multiplier for signed and unsigned numbers
26. Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra
27. Design and implementation of efficient Quaternary Signed Digit Multiplier
28. Faster and Low Power Twin Precision Multiplier
29. A Floating point Fused Dot Product Unit
30. Hardware modeling of binary coded decimal adder in field programmable gate array
31. Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag
32. Implementation of Area Efficient 16bit Adder in FPGA
33. An Efficient FPGA implementation of Double Precision floating Point Multiplier
34. Single phase clock distribution using VLSI technology for low power
35. Implementation of Power Efficient Vedic Multiplier using DBNS
36. A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm
37. Measurement and evaluation of power analysis attacks on Asynchronous S-Box
38. Platform-Independent Customizable UART Soft-Core
39. VLSI Implementation of OLS encoders
40. Implementation of Bus Bridge between AHB and OCP
41. FPGA Implementation of Booth’s and Baugh- Wooley Multiplier
42. FPGA Based High Speed Parallel Cyclic Redundancy Check
43. High Speed Booth Encoded Multiplier to Minimize the Computation time
44. Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation
45. Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA
46. A Novel Approach for parallel CRC generation FOR High Speed Application
47. VLSI design Of a Digital Clock Using GALS Technique
48. SCA-FF and SCAh-FF design for single cycle access test
49. A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using Spurious Power Suppression Technique
50. Design and implementation of a high performance multiplier using HDL
51. Design of Parallel Carry-Save Pipelined RSFQ Multiplier
52. Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR Algorithm
53. Efficient Weighted Pattern Generation Technique with Low Hardware Overhead
54. LUT Optimization for Memory-Based Computation
55. Using Self-Immunity Technique 64-bit Register File Immunity Improvement
56. High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based wavelet Transform
57. Pulse Triggered Flip-Flop Design for low power
58. A Novel Nanometric Parity Preserving Reversible Vedic Multiplier
59. Design and Analysis of Low Power Parallel Prefix VLSI Adder
60. High Speed FPGA implementation of FIR Filters for DSP Applications
2. Multi bit Flip-Flop design for Area efficiency
3. Constant and high speed adder design using QSD number system
4. Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology
5. Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool
6. Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique
7. Implementation of JPEG2000 using DWT
8. High-Performance High-Valency Ling Adders
9. High speed vedic multiplier using barrel shifter
10. Design of FIR Filter Design Based on Faithfully Rounded Truncated MCM
11. Built in generation of functional broadside tests using a fixed hardware structure
12. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation.
13. A new approach to design fault coverage circuit with efficient hardware utilization for testing applications
14. A Common Boolean Logic(CBL) implementation for modified CSLA
15. Design of High Speed Vedic Square by using Vedic Multiplication Techniques
16. Realization of Basic Gates Using MUX in CMOS Design
17. MDC FFT/IFFT Processor With Variable Length
18. Short Bit-Width Twos Complement Multipliers
19. High speed carry save multiplier based linear convolution using Vedic mathematics
20. Implementation of OFDM System using IFFT and FFT
21. Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
22. A Verilog Model of Universal Scalable Binary Sequence Detector
23. Performance Evaluation of Complex Multiplier Using Advance Algorithm
24. FPGA Implementation of 2-D DCT Architecture for JPEG Image Compression
25. High speed Modified Booth Encoder multiplier for signed and unsigned numbers
26. Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra
27. Design and implementation of efficient Quaternary Signed Digit Multiplier
28. Faster and Low Power Twin Precision Multiplier
29. A Floating point Fused Dot Product Unit
30. Hardware modeling of binary coded decimal adder in field programmable gate array
31. Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag
32. Implementation of Area Efficient 16bit Adder in FPGA
33. An Efficient FPGA implementation of Double Precision floating Point Multiplier
34. Single phase clock distribution using VLSI technology for low power
35. Implementation of Power Efficient Vedic Multiplier using DBNS
36. A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm
37. Measurement and evaluation of power analysis attacks on Asynchronous S-Box
38. Platform-Independent Customizable UART Soft-Core
39. VLSI Implementation of OLS encoders
40. Implementation of Bus Bridge between AHB and OCP
41. FPGA Implementation of Booth’s and Baugh- Wooley Multiplier
42. FPGA Based High Speed Parallel Cyclic Redundancy Check
43. High Speed Booth Encoded Multiplier to Minimize the Computation time
44. Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation
45. Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA
46. A Novel Approach for parallel CRC generation FOR High Speed Application
47. VLSI design Of a Digital Clock Using GALS Technique
48. SCA-FF and SCAh-FF design for single cycle access test
49. A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using Spurious Power Suppression Technique
50. Design and implementation of a high performance multiplier using HDL
51. Design of Parallel Carry-Save Pipelined RSFQ Multiplier
52. Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR Algorithm
53. Efficient Weighted Pattern Generation Technique with Low Hardware Overhead
54. LUT Optimization for Memory-Based Computation
55. Using Self-Immunity Technique 64-bit Register File Immunity Improvement
56. High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based wavelet Transform
57. Pulse Triggered Flip-Flop Design for low power
58. A Novel Nanometric Parity Preserving Reversible Vedic Multiplier
59. Design and Analysis of Low Power Parallel Prefix VLSI Adder
60. High Speed FPGA implementation of FIR Filters for DSP Applications
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